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ver.5 NJW1321 -1- wide band video switch with i 2 c bus general description package outline the NJW1321 is a wide band video switch with i 2 c bus. the NJW1321 includes switch of 4-input 2-output and 6db amplifier. it is suitable for rgb or y, pb, and pr signal because frequency range is 100mhz. the NJW1321 includes external logic control terminals and external logic discernment terminals. the NJW1321 is suitable for ptv, dtv, pdp and other high quality av systems. features operating voltage +9.0v i 2 c bus interface 4-input 2-output 3-circuits wide frequency range 0db at 100mhz typ. -3db at 300mhz typ. internal 6db amplifier (selectable bypass or 6db) external logic discernment terminal external logic control terminal selectable slave address power save circuit bi-cmos technology package outline qfp48 block diagram NJW1321fp1 6db 6db 6db 6db 6db 6db i 2 c bus y/r in1 y/r in2 y/r in3 y/r in4 pb/g in1 pb/g in2 pb/g in3 pb/g in4 pr/b in1 pr/b in2 pr/b in3 pr/b in4 y/r out1 y/r out2 pb/g out1 pb/g out2 pr/b out1 pr/b out2 address sda scl v+ gnd aux 0 aux 1 aux 2 aux 3 port 0 port 1 port 2 port 3 vref bias dgnd
NJW1321 - 2 - pin configuration 1. v+ 13. port2 25. aux0 37. v+ 2. pb in2 14. adr 26. aux1 38. pb in4 3. gnd 15. scl 27. y out2 39. gnd 4. pr in2 16. sda 28. aux2 40. pr in4 5. gnd 17. gnd 29. aux3 41. v+ 6. y in1 18. dgnd 30. pr out1 42. y in3 7. v+ 19. vreg 31. gnd 43. gnd 8. pb in1 20. v+ 32. pb out1 44. pb in3 9. v+ 21. pr out2 33. gnd 45. v+ 10. pr in1 22. port1 34. y out1 46. pr in3 11. gnd 23. port 0 35. v+ 47. gnd 12. port3 24. pb out2 36. y in4 48. y in2 v + gnd v+ pb in2 pr in2 y in1 pb in1 pr in1 port3 v+ adr port2 gnd scl sda dgnd vref v+ pr out2 port1 port0 pb out2 1 14 38 25 39 24 48 15 y in2 gnd pr in3 v+ pb in3 gnd y in3 v+ pr in4 gnd gnd a ux0 a ux1 y out2 a ux2 a ux3 pr out1 gnd pb out1 gnd y out1 v+ y in4 v+ pb in4 gnd
NJW1321 -3- absolute maximum ratings (ta=25 c) parameter symbol ratings unit supply voltage v + 12.0 v power dissipation p d 1875(note) mw operating temperature range topr -40 to +75 c storage temperature range tstg -40 to +150 c (note) at on a board of eia/jedec specification. (76.2 114.3 1.6mm two layers, fr-4) recommended opearating condition (ta=25 c) parameter symbol test condition min. typ. max. unit operating voltage vopr 8.5 9.0 9.5 v electrical characteristics (v + =9.0v, r l =10k ? , ta=25 c) video parameter symbol test condition min. typ. max. unit operating current i cc no signal - 85 100 ma maximum output voltage vom f=100khz, thd=1% 2.0 2.5 - vp-p voltage gain 1 gv1 6db mode vin=100khz, 1.0vp-p sin signal 6.0 6.4 6.8 db voltage gain 2 gv2 bypass mode vin=100khz, 1.0vp-p sin signal -0.5 0.0 0.5 db frequency characteristic 1 gf1 6db mode vin=100mhz / 100khz, 1.0vp-p sin signal - 0 - db frequency characteristic 2 gf2 bypass mode vin=100mhz / 100khz, 1.0vp-p sin signal - 0 - db frequency characteristic 3 gf3 6db mode vin=300mhz / 100khz, 1.0vp-p sin signal - -3.0 - db frequency characteristic 4 gf4 bypass mode vin=300mhz / 100khz, 1.0vp-p sin signal - -3.0 - db cross talk 1 ctb1 vin=4.43mhz,1.0vp-p sin signal - -60 -50 db cross talk 2 ctb2 vin=50mhz,1.0vp-p sin signal - -40 - db differential gain dg vin=1.0vp-p 10step video signal - 0.3 - % differential phase dp vin=1.0vp-p 10step video signal - 0.3 - deg s/n snv vin=1.0vp-p,100% white video signal - 65 - db port, aux parameter symbol test condition min. typ. max. unit port input voltage h v pth 3.5 - 5.5 v port input voltage m v ptm 1.4 - 2.4 v pory input voltage l v ptl 0 - 0.8 v aux output voltage h v auxh 3.5 - 5.5 v aux output voltage m v auxm 1.4 - 2.4 v aux output voltage l v auxl 0 - 0.8 v adr input voltage h v adrh 3.5 - 5.0 v adr input voltage l v adrl 0 - 1.0 v
NJW1321 - 4 - sda scl t f t hd:st a t low t r t hd:dat t high t f t su:dat s t su:sta t hd:st a t sp t su:sto sr t r t buf p s i 2 c bus block characteristics (sda,scl) i 2 c bus load conditions standard mode: pull up resistance 4k ? (connected to +5v), load capacitance 200pf (connected to gnd) parameter symbol min typ max unit low level input voltage v il 0.0 - 1.5 v high level input voltage v ih 2.7 - 5.5 v low level output voltage (3ma at sda pin) v ol 0 - 0.4 v output fall time from v ihmin to v ilmax with a bus capacitancefrom 10pf to 400pf t of - - 250 ns input current each i/o pin with an input voltage between 0.1 and 0.9v ddmax i i -10 - 10 a capacitance for each i/o pin c i - - 10 pf scl clock frequency f scl - - 100 khz data transfer start minimum waiting time t hd:sta 4.0 - - s low level clock pulse width t low 4.7 - - s high level clock pulse width t high 4.0 - - s minimum start preparation waiting time t su:sta 4.7 - - s minimum data hold time t hd:dat 0 - - s minimum data preparation time t su:dat 250 - - ns rise time t r - - 1000 ns fall time t f - - 300 ns minimum stop preparation waiting time t su:sto 4.0 - - s data change minimum waiting time t buf 4.7 - - s capacitive load for each bus line c b - - 400 pf noise margin at the low level v nl 0.5 - - v noise margin at the high level v nh 1 - - v c b ; total capacitance of one bus line in pf.
NJW1321 -5- equivalent circuit pin no. name function inside equivalent circuit voltage 6 8 10 48 2 4 42 44 46 36 38 40 y in1 pb in1 pr in1 y in2 pb in2 pr in2 y in3 pb in3 pr in3 y in4 pb in4 pr in4 y,pb,pr input rgb input 4.4v 34 32 30 27 24 21 y out1 pb out1 pr out1 y out2 pb out2 pr out2 y, p b , p r o u t p u t rgb output 3.7v 23 22 13 12 port0 port1 port2 port3 logic input terminal - 25 26 28 29 aux0 aux1 aux2 aux3 auxiliary 3 values voltage output terminal 0v 1.9v 5.0v v + 100 ? 150k ? v + v + v + v + 50 ? 100k ? 66 ? v + v + 66 ? v + v + v + 1k ?
NJW1321 - 6 - pin no. name function inside equivalent circuit voltage 14 adr slave address setting terminal - 15 16 scl sda i 2 c clock terminal i 2 c data terminal - 19 vref reference voltage terminal 4.8v 1 7 9 20 35 37 41 45 v+ supply voltage terminal - 3 5 11 17 31 33 39 43 47 gnd ground terminal - 18 dgnd ground terminal - vref 66 ? v + v + 4k ? 66 ? v + v + v + 48k ?
NJW1321 -7- definition of i 2 c register ? ? ? ? i 2 c bus format msb lsb msb lsb msb lsb s slave address a data a data a p 1bit 8bit 1bit 8bit 1bit 8bit 1bit 1bit s: starting term a: acknowledge bit p: ending term ? ? ? ? slave address r/w: set the write mode or read mode. adr : set the slave address by ?adr? terminal. slave address hex msb lsb - 1 0 0 0 0 0 adr r/w - r/w = 0 : write mode, adr = 0/1 - 1 0 0 1 0 1 0 0 94(h) 1 0 0 1 0 1 1 0 96(h) r/w = 1 : read mode, adr = 0/1 - 1 0 0 1 0 1 0 1 95(h) 1 0 0 1 0 1 1 1 97(h) ? ? ? ? control register table < write mode > bit no. d7 d6 d5 d4 d3 d2 d1 d0 data1 ps1 ps2 out1 out2 data2 aux0 aux1 aux2 aux3 < read mode > bit no. d7 d6 d5 d4 d3 d2 d1 d0 data port0 port1 port2 port3 ? ? ? ? control register default value control register default value is all ?0?. bit no. d7 d6 d5 d4 d3 d2 d1 d0 data1 0 0 0 0 0 0 0 0 data2 0 0 0 0 0 0 0 0
NJW1321 - 8 - ? instruction code ? ? ? ? power save, output setting bit no. d7 d6 d5 d4 d3 d2 d1 d0 data1 ps1 ps2 out1 out2 ? ? ? ? ps1, ps2: power save setting power save d7 d6 out1 on out2 on 0 0 out1 on out2 off 0 1 out1 off out2 on 1 0 out1 off out2 off 1 1 on: power save off, off: power save on (mute) ? ? ? ? out1: output 1 setting output 1 d5 d4 yin1 pbin1 prin1 0 0 yin2 pbin2 prin2 0 1 yin3 pbin3 prin3 1 0 yin4 pbin4 prin4 1 1 ? ? ? ? out2: output 2 setting output 2 d2 d1 yin1 pbin1 prin1 0 0 yin2 pbin2 prin2 0 1 yin3 pbin3 prin3 1 0 yin4 pbin4 prin4 1 1 gain d3 6db 0 0db 1 gain d0 6db 0 0db 1
NJW1321 -9- ? ? ? ? aux: auxiliary setting bit no. d7 d6 d5 d4 d3 d2 d1 d0 data2 aux0 aux1 aux2 aux3 aux0 d7 d6 l 0 0 m 0 1 h 1 1 aux1 d5 d4 l 0 0 m 0 1 h 1 1 aux2 d3 d2 l 0 0 m 0 1 h 1 1 aux3 d1 d0 l 0 0 m 0 1 h 1 1 ? ? ? ? port: port setting bit no. d7 d6 d5 d4 d3 d2 d1 d0 data port0 port1 port2 port3 port0 d7 d6 open 0 0 l 0 0 m 0 1 h 1 1 port1 d5 d4 open 0 0 l 0 0 m 0 1 h 1 1 port2 d3 d2 open 0 0 l 0 0 m 0 1 h 1 1 port3 d1 d0 open 0 0 l 0 0 m 0 1 h 1 1
NJW1321 - 10 - test circuit + + 10k ? 10uf + 0.1uf 50 ? /75 ? 1uf 0.1uf + 100uf + 0.1uf 1uf + + + + + + + 10uf + 0.1uf 10k ? pr in4 pr in3 1uf + 0.1uf pb in2 pr in2 y in1 pb in1 pr in1 port2 port0 port3 sda adr scl aux0 aux1 y out2 y out1 pr out1 pr out2 pb out1 y in4 v+ njw1320 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 15 16 17 18 19 20 21 22 23 24 1 2 3 4 5 6 7 9 10 11 12 13 14 y in3 + 8 + port1 pb out2 aux2 aux3 1uf + 1uf + pb in4 + pb in3 + y in2 NJW1321 50 ? /75 ? 0.1uf 1uf 50 ? /75 ? 0.1uf 1uf 50 ? /75 ? 0.1uf 1uf 50 ? /75 ? 0.1uf 1uf 1uf 0.1uf 1uf 0.1uf 50 ? /75 ? 50 ? /75 ? 50 ? /75 ? 50 ? /75 ? 50 ? /75 ? 1uf 0.1uf 1uf 0.1uf 10k ? 10uf 0.1uf 10k ? 10k ? 10k ? 10k ? 10k ? 10k ? 10k ? 10uf 0.1uf 10uf 0.1uf 10uf 0.1uf 0.1uf 0.1uf 50 ? /75 ? 50 ? /75 ?
NJW1321 -11- application circuit + + 10uf + 0.1uf 75 ? 1uf 0.1uf + 100uf + 0.1uf 1uf + + + + + + + 10uf + 0.1uf 10k ? pr in4 pr in3 1uf + 0.1uf pb in2 pr in2 y in1 pb in1 pr in1 port2 port0 port3 sda adr scl aux0 aux1 y out2 y out1 pr out1 pr out2 pb out1 y in4 v+ njw1320 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 15 16 17 18 19 20 21 22 23 24 1 2 3 4 5 6 7 9 10 11 12 13 14 y in3 + 8 + port1 pb out2 aux2 aux3 1uf + 1uf + pb in4 + pb in3 + y in2 NJW1321 0.1uf 1uf 0.1uf 1uf 0.1uf 1uf 0.1uf 1uf 1uf 0.1uf 1uf 0.1uf 1uf 0.1uf 1uf 0.1uf 10uf 0.1uf 10k ? 10k ? 10k ? 10uf 0.1uf 10uf 0.1uf 10uf 0.1uf 0.1uf 0.1uf 75 ? 75 ? 75 ? 75 ? 75 ? 75 ? 75 ? 75 ? 75 ? 75 ? 75 ?
NJW1321 - 12 - typical characteristics note please all connect v+ terminal and gnd terminal. when the power supply voltage is not impressing, please do not impress voltage to the adr terminal. -40 -30 -20 -10 0 10 voltege gain vs. frequency 0db 6db 10 6 10 7 10 8 gv[db] frequency[hz] [caution] the specifications on this databook are only given for information , without any guarantee as regards either mistakes or omissions. the application circuits in this databook are described only to show representative usages of the product and not intended for the guarantee or permission of any right including the industrial rights.

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